1. Field of the Invention
The invention relates to semiconductor device processes, and more particularly, to improved methods for etching openings in insulating layers and a semiconductor device with well defined contact openings.
2. Background of the Invention
In the fabrication of semiconductor devices, numerous conductive device regions and layers are formed in or on a semiconductor substrate. The conductive regions and layers of the device are isolated from one another by a dielectric. Examples of dielectrics include silicon dioxide, SiO.sub.2, tetraethyl orthosilicate glass ("TEOS"), silicon nitrides, Si.sub.x N.sub.y, silicon oxynitrides, SiO.sub.x N.sub.y (H.sub.z), and silicon dioxide/silicon nitride/silicon dioxide ("ONO"). The dielectrics may be grown, or may be deposited by physical deposition (e.g., sputtering) or by a variety of chemical deposition methods and chemistries (e.g., chemical vapor deposition ("CVD")). Additionally, the dielectrics may be undoped or may be doped, for example with boron, phosphorous, or both, to form, for example, borophosphosilicate glass ("BPSG"), phosphosilicated glass ("PSG"), and borophosphosilicate tetraethyl orthosilicate glass ("BPTEOS").
At several stages of the fabrication of semiconductor devices, it is necessary to make openings in the dielectric to allow for contact to underlying regions or layers. Generally, an opening through a dielectric exposing a diffusion region or an opening through a dielectric layer between polysilicon and a first metal layer is called a "contact opening", while an opening in other oxide layers such as an opening through an intermetal dielectric layer is referred to as a "via". For purposes of the claimed invention, henceforth "contact opening" or "contact region" will be used to refer to contact openings and/or via. The opening may expose a device region within the silicon substrate, such as a source or drain, or may expose some other layer or structure, for example, an underlying metallization layer, local interconnect layer, or structure such as a gate. After the opening has been formed exposing a portion of the region or layer to be contacted, the opening is generally cleaned with a sputter etch, e.g., a Radio-Frequency ("RF") sputter etch, and then the opening is filled with a conductive material deposited in the opening and in electrical contact with the underlying region or layer.
To form the openings a patterning layer of photoresist is first formed over the dielectric layer having openings corresponding to the regions of the dielectric where the dielectric layer openings are to be formed. In most modern processes a dry etch is then performed wherein the wafer is exposed to a plasma, formed in a flow of one or more gases. Typically, one or more halocarbons and/or one or more other halogenated compounds are used as the etchant gas. For example, CF.sub.4, CHF.sub.3 (Freon 23), SF.sub.6, NF.sub.3, and other gases may be used as the etchant gas. Additionally, gases such as O.sub.2, Ar, N.sub.2, and others may be added to the gas flow. The particular gas mixture used will depend on, for example, the characteristics of the dielectric being etched, the stage of processing, the etch tool being used, and the desired etch characteristics, i.e., etch rate, sidewall slope, anisotropy, etc.
Many of the etch characteristics are generally believed to be affected by polymer residues that deposit during the etch. For this reason, the fluorine to carbon (F/C) ratio in the plasma is considered an important determinant in the etch. In general, a plasma with a high F/C ratio will have a faster etch rate than a plasma with a low F/C ratio. At very low rates, i.e., high carbon content, polymer deposition occurs and etching ceases. The etch rate as a function of the F/C ratio is typically different for different materials. The difference is used to create a selective etch, by using a gas mixture that puts the F/C ratio in the plasma at a value that leads to etching at a reasonable rate for one material, and that leads to no etching or polymer deposition for another. For example, an etchant that has an etch rate ratio or a selectivity ratio of two to one for silicon nitride compared to silicon dioxide is an effective stripper of silicon nitride from the semiconductor substrate, because it will selectively strip silicon nitride over silicon dioxide on a substrate surface. An etchant that has an etch rate ratio or a selectivity ratio of 0.85 to one for silicon nitride compared to silicon dioxide is not considered an effective stripper of silicon nitride from the semiconductor substrate because the etchant will not effectively strip silicon nitride to the exclusion of silicon dioxide.
The selectivity of the etch process is a useful parameter for monitoring the process based on the etch rate characteristic of the particular etchant. As noted above, particular etchants or etchant chemistries attack different materials at different etch rates. With respect to dielectrics, for example, particular etchants attack silicon dioxide, BPTEOS, TEOS, and silicon nitride dielectrics at different rates. To make openings in a substrate comprising a contact region surrounded by different dielectric layers, e.g., a dielectric layer of TEOS surrounded by a dielectric layer of silicon nitride, a process will utilize different etchants to make openings through the different dielectrics. Thus, the different etch rates of particular dielectric layers for an etchant may be used to monitor the creation of an opening through a dielectric layer.
Further, by adjusting the feed gases, the taper of the sidewall in the etched opening of the dielectric can be varied. If a low sidewall angle is desired, the chemistry is adjusted to try to cause some polymer buildup on the sidewall. Conversely, if a steep sidewall angle is desired, the chemistry is adjusted to try to prevent polymer buildup on the sidewall. Varying the etch gas pressure, for example, has a significant effect on the shape of the opening. This is because the etchant ions generally arrive in a direction perpendicular to the substrate surface, and hence strike the bottom surfaces of the unmasked substrate. The sidewalls of etched openings, meanwhile, are subjected to little or no bombardment. By increasing the pressure of the etch gas, the bombardment directed toward the sidewalls is increased; by decreasing the pressure of the etch gas, the bombardment directed toward the sidewalls is decreased. The changing of the etch chemistry is also directly related to selectivity. Etchants that provide a near 90.degree. sidewall angle are generally not highly selective while highly selective etches typically produce a sloped sidewall.
Following the dielectric etch(es) and prior to any conductive material deposition in a contact region, native oxide on top of the conducting layers in the contact region is removed or cleaned through a non-chemical sputter etch, e.g., an RF sputter etch. In addition to alleviating the contact region of native oxide, the sputter etch can erode any insulating dielectric layer or layers. Thus, the parameters of the sputter etch must be carefully monitored so as not to excessively erode the insulating dielectric layer(s) and expose other underlying conductive material. Exposing insulated conductive material adjacent to the conductive material in the contact region results in poor quality contacts or a short circuit through the underlying conductive material. For a thorough discussion of oxide etching, see S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era, Vol. 1, pp. 539-85 (1986).
The preceding discussion focused on the making of openings, e.g., contact openings, in dielectric material on a semiconductor substrate. The same principles are used in constructing device regions with a dielectric layer or layers. As geometries shrink, the forming of discrete devices on a semiconductor substrate becomes more specialized. Specialized deposition and etching techniques permit the density of semiconductor elements on a single chip to greatly increase, which translates into larger memory, faster operating speeds, and reduced production costs.
A typical metal oxide semiconductor (MOS) transistor, e.g., NMOS or PMOS transistor, generally includes source/drain regions in a substrate, and a gate electrode formed above the substrate between the source/drain regions and separated from the substrate by a relatively thin dielectric. Contact structures can be inserted to the source/drain regions and interlays can overlie the contact structures and connect neighboring contact structures. These contact structures to the diffusion region are isolated from the adjacent gate by dielectric spacer or shoulder portions. The dielectric spacer or shoulder portions also isolate the gate from the diffusion region.
Conventional contact structures limit the area of the diffusion region, because the contact hole is aligned to these regions with a separate masking step, and extra area must be allocated for misalignment. Proper alignment is necessary to avoid shorting the contact structure to the gate or the diffusion well. The larger contact area means a smaller density of elements on a structure. The larger contact area is also responsible for increased diffusion-to-substrate junction capacitance, which limits device speed.
A self-aligned contact eliminates the alignment problems associated with conventional contact structures and increases the device density of a structure. A self-aligned contact is a contact to a source or drain diffusion region. A self-aligned contact is useful in compact geometries because it can overlap a conducting area to which it is not supposed to make electrical contact and can overlap the edge of a diffusion region without shorting out to the well beneath. Consequently, less contact area is needed and gates or conductive material lines, e.g., polysilicon lines, can be moved closer together allowing more gates or lines on a given substrate than traditional contacts.
FIG. 1 illustrates a self-aligned contact 130 between two gate structures. FIG. 1(A) is a planar top view of the contact 130. FIG. 1(B) is a planar cross-sectional view of the self-aligned contact 130 between a pair of gates taken through line 1(B) of FIG. 1(A). FIG. 1(C) is a planar cross-sectional view of the self-aligned contact 130 between a pair of gates taken through line 1(C) of FIG. 1(A).
The self-aligned contact 130 is a contact to a source or drain diffusion region (n+ or p+ silicon) 140 that can overlap a edge of the diffusion region 140 without shorting out to a well beneath the diffusion region 140. This can be seen most illustratively through FIG. 1(C). In FIG. 1(C), the contact 130 does not lie directly in the diffusion region 140, but is misaligned and slightly overlaps the field oxide (designated by FOX in FIG. 10. In this illustration, the self-aligned contact 130 is not directly over the diffusion region but extends over (i.e., overlaps) a well portion 170. The self-aligned contact 130 does not short to the well portion 170 because the self-aligned contact 130 is separated from the well 170 by the field oxide.
The self-aligned contact 130 is separated from a conducting polysilicon layer 110 by an encapsulating dielectric layer 120 such that the contact 130 can also overlap the polysilicon layer 110 without making electrical contact to the layer 110 or gate. The polysilicon layer 110 is separated from the source/drain diffusion region 140 by a dielectric spacer or shoulder 150 of the same or different dielectric material as the dielectric layer 120 directly above the conducting polysilicon layer 110.
A distinct dielectric etch stop layer 125 overlies the encapsulating dielectric layer 120. The etch stop layer 125 permits subsequent etching of the substrate without risk of exposing the device structures and layers because the device structuring and layers are protected from excessive etching by the etch stop layer 125. The diffusion contact is self-aligning because the structure can be etched to the substrate over the source/drain diffusion region 140 while the dielectric spacer 150 protects the polysilicon layer 110. Even if a photoresist that protects the polysilicon layer 110 from the etchant is misaligned with respect to the polysilicon layer 110, the dielectric spacer 150 prevents shorts to the polysilicon layer 110 when the contact 130 is provided for the diffusion region 140.
The current practice with respect to forming contact regions, particularly self-aligned contact regions, that are in electrical contact with gates, interconnect lines, or other structures in small feature size structures is to utilize etchants with high selectivity to protect underlying regions, like the etch stop layer and the first insulating layer. FIG. 2 illustrates a typical prior art process of forming a self-aligned contact region adjacent to a gate. In FIG. 2(A), a gate oxide layer 210 is formed on a substrate 200 with a conducting layer, for example a polysilicon layer 220, overlying the gate oxide layer 210, and an insulating layer, for example a TEOS layer 230, overlying the polysilicon layer 220. Adjacent to the polysilicon layer 220 is a contact opening region 270. The polysilicon layer 220 is separated from the contact region 270 by an insulating spacer portion, for example a TEOS spacer portion 235. A separate insulating or etch stop layer, for example a silicon nitride layer 240 overlies the TEOS layer 230 and the contact region 270. A blanket layer, for example a doped insulating layer like a BPTEOS layer 270, planarly overlies the etch stop layer 240.
A layer of photoresist material 280 overlies the planarized BPTEOS layer 250 to expose the contact opening 270. In FIG. 2(A), a contact opening 270 has been opened through the BPTEOS layer 250. The etchant utilized to make the opening had a high selectivity toward BPTEOS relative to silicon nitride. When the contact opening 270 was formed through the BPTEOS material, the etchant did not etch or did not effectively etch the silicon nitride layer 240 material. Hence, the silicon nitride layer 240 is described as an etch stop layer. The silicon nitride etch stop layer 240 protected the underlying TEOS layer 230 and spacer portion 235 so that the polysilicon layer 220 remained completely encapsulated.
FIG. 2(A) illustrates an etch 260 to remove the silicon nitride etch stop layer 240. In the etch 260 illustrated in FIG. 2(A), a high selectivity etch toward silicon nitride relative to the underlying TEOS layer 230 material is practiced to efficiently etch the silicon nitride layer 240 and to protect the underlying TEOS layer 230 from the etchant. An example of a high selectivity etch recipe to effectively strip silicon nitride as compared to the TEOS layer is 30 sccm CHF.sub.3 and 30 sccm O.sub.2 at 60 mtorr and 100 watts of power. The result of the high selectivity etch is illustrated in FIG. 2(B).
FIG. 2(B) shows that the silicon nitride selective etch effectively removed silicon nitride layer 240 from the contact opening 270. The selective etch for silicon nitride compared to TEOS material, however, left the TEOS layer 230 with a spacer portion 235 wherein the spacer portion 235 is sloping or tapered toward the contact opening 270. This result follows even where the spacer portion 235 is originally substantially rectangular as in FIG. 2(A). The properties of the highly selective etch of the overlying etch stop layer 240 will transform a substantially rectangular spacer into a sloped spacer. FIG. 2(B) presents a polysilicon layer 220 encapsulated in a TEOS layer 230 with a spacer portion 235 adjacent to the contact opening 270, the spacer portion 235 having an angle 290 that is less than 85.degree..
In addition to providing stopping points or selectivity between materials, the use of high selectivity etches to form sloped spacer portions is the preferred practice because the sloped shape will result in good step coverage by the metal that is deposited into it. The filling of contact openings or gaps (i.e., gap fill) is an important consideration because it relates directly to the reliability of a device. If an opening is not completely filled with an insulative material, for example, and a gap is created, a subsequent conductive material deposit can fill the gap which can lead to shorting. Sloped contact openings are easier to completely fill than boxy structures because the transition between sloped structures and openings is smooth compared to the abrupt transitions between boxy structures and openings. Because of concerns for complete gap fill and good step coverage, industry preference is for sloped spacers and planar deposition layers similar to that shown in FIG. 2(b).
Once the contact opening is made, the opening is cleaned with a sputter etch, e.g., an RF sputter etch, before conductive material is added to fill the opening or gap. The RF sputter etch that is used to clean the contact opening in the process described above will attack and erode a portion of the insulating spacer surrounding the conducting portion and adjacent to the contact region. FIG. 3 illustrates a prior art substrate with a gate and a contact region undergoing an RF sputter etch 380. In FIG. 3, a gate oxide 310 is formed on a substrate 300 with a polysilicon layer 320 overlying the gate oxide 310 and an insulating layer, for example a TEOS layer 330 overlying the polysilicon layer 320. A distinct insulating layer, for example a silicon nitride etch stop layer 340, overlies the TEOS layer 330 and this etch stop layer 340 is covered by a third insulating layer, for example a BPTEOS blanket layer 350. Adjacent to the gate is a contact region 360. An etch of the silicon nitride etch stop layer 340 with a high selectivity etch for silicon nitride relative to the underlying TEOS layer material produced a gate with a sloping or tapered spacer portion 370 of TEOS material, illustrated in ghost lines. A subsequent RF sputter etch 380 is utilized to clean the contact region 360. Although brief and designed to clean the contact region, the RF sputter etch 380 will erode a portion of the insulating TEOS spacer portion 370. The dynamics of the sputter etch are that it proceeds vertically, directing high-energy particles at the contact region. The sloping or tapered spacer portion 370 adjacent the polysilicon layer 320 and separating the polysilicon from the layer 320 contact region 360 is struck by the high-energy particles of the RF sputter etch 380. Because the spacer portion 370 is sloping or diagonal, a significant surface area portion of the spacer portion 370 is directly exposed to the high-energy particles from the RF sputter etch 380. Further, with sloping spacers, or spacers having an angle relative to the substrate surface of less than 85.degree. the vertical portion of the dielectric layer (i.e., that portion above the polysilicon layer 320) decreases much less than the diagonal portion of the spacer. In terms of measuring TEOS material removal during the RF sputter etch 380 in FIG. 3, the difference between d.sub.1 and d.sub.2 is greater than the difference between v.sub.1 and v.sub.2. Thus, in conventional prior art self-aligned contact structures, the diagonal thickness of the TEOS spacer, portion 370 rather than the vertical thickness of the TEOS layer 330, determines the minimum insulating layer thickness for the gate.
For gate structures having minimum diagonal insulative spacer portions of 500 .ANG. or less, the result of the sputter etch 380 is that the sputter etch 380 laterally erodes the diagonal portion of the TEOS spacer portion 370 adjacent to the contact region to a point where the polysilicon layer 320 is no longer isolated from the contact region 360 by an insulating layer. In that case, there is a short circuit through the underlying conductive material when the contact region 360 is filled with conductive material. This result follows because the conventional RF sputter etch 380 utilized for cleaning the contact region 360 results in an approximately 200-500 .ANG. loss of the spacer material. Further, process margins generally require that the device spacer have a final minimum thickness (after all etches, doping, and deposits) of at least 500 .ANG.. Thus, to eliminating alignment sensitivity for conventional small feature size structures, including self-aligned contact structures, requires a final (i.e., at the time of contact deposition) minimum insulating spacer of more than 500 .ANG. and preferably on the order of 1000-1500 .ANG. or greater to fulfill requirements for an adequate process margin, complete gap fill, and device reliability.
To construct structures having a minimum insulative spacer portion of more than 500 .ANG. directly effects the number of structures that can be placed on a device, such as a chip. The construction of structures having a minimum insulative spacer portion of more than 500 .ANG. requires that the pre-etch-stop-etch spacer be bigger or thicker to yield an effective spacer after the etching processes. In such cases, the structures must be separated a distance such that the contact area opening is sufficient enough for an effective contact. This spacing requirement directly limits the number of structures that can be included on a device. In small feature size structures, particularly structures utilizing self-aligned contacts, the width of contact openings is approximately 0.6 microns at the top of the planarized layer and 0.2 microns at the base of the contact opening. FIG. 3 indicates the difference in contact opening widths for the same contact in prior art structures. w.sub.1 represents the width at the top of the planarized layer and w.sub.2 represents the width at the base of the contact region 360. Further, an aspect ratio can be defined as the height of a structure (field oxide plus conductive layer plus first insulative layer plus etch stop layer, if any) relative to the width of the base of a contact opening (i.e., the distance between adjacent spacers). Typical aspect ratios for self-aligned contact structures target ratios of 1.0-2.4. This prior art range is not achievable with any device reliability. To achieve aspect ratios of 1.0-2.4 requires minimum spacer portions of less than 1000 .ANG. and preferably on the order of 500 .ANG.. As noted above, the minimum spacer portions required for aspect ratios of 1.0-2.4 cannot withstand the sputter etch and will result in the exposure of the underlying polysilicon gate and short circuiting with the contact.
There is a need for cost effective structures wherein the individual devices are as close together as possible while maintaining device reliability and an adequate process margin and assuring complete gap fill. There is a need for a device and for a process to manufacture such a device whereby there is provided a contact opening with no alignment sensitivity relative to a gate electrode or other structure and whereby the gate electrode does not fall within the contact opening but remains isolated from the contact opening by an insulating layer. The process must be compatible with gate electrode insulating spacers of less than 500 .ANG.. The device resulting from the needed process should be capable of maintaining high quality contacts between the conductive material in the contact region and the adjacent conductive gate or other structure.